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• W90263273 abstract "Abstract This paper intends to show how to build up a testability model from a VHDL data flow description. This model, which describes the information transfers through the considered hardware part, is then used by a testability analysis system. A first step consists in translating the VHDL description into a set of expressions isomorphic to the information transfer model. This allows to define rewriting rules which have the same effect on the expressions as on the model. In a second part, we present the signal dependency analysis whose aim is to identify the dependency cycles. Then, two simplification phases are performed. The first one consists in evaluating the constants and simplifying the expressions according to the identity and absorbent elements. The second one aims at identifying the expressions in order to match identical places in the resulting graph. A last step consists in correcting the resulting information transfer model according to the notion of information quantity." @default.
• W90263273 created "2016-06-24" @default.
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• W90263273 date "1991-01-01" @default.
• W90263273 modified "2023-09-24" @default.
• W90263273 title "Using a VHDL description to generate hardware test" @default.
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• W90263273 doi "https://doi.org/10.1016/b978-0-444-89208-9.50031-4" @default.
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