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- W938634053 abstract "This chapter begins with examples that demonstrate how commercially available intellectual property cores can be embedded in different designs. In particular, arithmetical circuits constructed from digital signal processing slices, and parameterized memory blocks that provide support for data buffering (such as FIFO—first input first output), are described. More details on digital signal processing slices are then given and it is shown how these may be used efficiently in practical circuits such as Hamming weight counters/comparators. The major part of this chapter is dedicated to interactions between a host computer and FPGA-based prototyping boards through the Digilent enhanced parallel port and the UART (Universal Asynchronous Receiver and Transmitter) interfaces. Complete details of the communication modules are described, including both software for general-purpose computers that was developed in the C++ language, and hardware for FPGAs. The next section makes use of the designed modules for projects that involve such interactions for different purposes. A more complicated design for a network-based iterative data sorter from Chap. 3 is implemented and tested in this way as a complete fully functioning example. The chapter concludes with a brief description of programmable systems-on-chip (PSoC) that combine an embedded processing system with a reconfigurable logic which can lead to more efficient implementations of the applications. Proposals for mapping the designs from Chap. 3 to the PSoC are given and discussed." @default.
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- W938634053 date "2014-01-01" @default.
- W938634053 modified "2023-09-26" @default.
- W938634053 title "Embedded Blocks and System-Level Design" @default.
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- W938634053 doi "https://doi.org/10.1007/978-3-319-04708-9_4" @default.
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