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- W963977683 abstract "This tutorial paper gives a functional semantics for delta-delay VHDL, i.e. VHDL restricted to zero-delay signal assignments. In combination with the sequential statements zero-delay signal assignment is sufficient to generate the full algorithmic expressibility of VHDL. The restriction is useful for a formal semantics of VHDL aimed at higher levels of abstraction where real, absolute, and precise timing often is painful if not impossible to prescribe.The approach employs the functional specification methodology Focus which is based on the concept of streams and stream-processing functions. It advocates a three-level semantics reflecting VHDL’s three syntactic levels of expressions, statements, and processes.KeywordsSequential StatementResolution FunctionFormal SemanticInput StreamOutput StreamThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves." @default.
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- W963977683 date "1995-01-01" @default.
- W963977683 modified "2023-10-16" @default.
- W963977683 title "A Functional Semantics for Delta-Delay VHDL Based on Focus" @default.
- W963977683 doi "https://doi.org/10.1007/978-1-4615-2237-9_2" @default.
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